8-bit shift register vhdl code

The translation of VHDL into Chinese is the ultra-high-speed integrated circuit hardware description language, which is mainly used in the design of digital circuits. Most of its applications in China are used in the design of FPGA/CPLD/EPLD. Of course, in some of the more powerful units, it is also used to design ASIC.

VHDL is mainly used to describe the structure, behavior, functions and interfaces of digital systems. In addition to containing many statements with hardware features, VHDL's language form, description style, and syntax are very similar to general computer high-level languages. The program structure of VHDL is characterized by dividing an engineering design, or design entity (which can be a component, a circuit module or a system) into an external (or visual part, and port) and an internal (or invisible part). , both the internal functions of the entity and the algorithm completion part. After defining an external interface to a design entity, once the internal development is complete, other designs can call the entity directly. This concept of dividing the design entity into internal and external parts is the basic point of VHDL system design.

VHDL has a powerful language structure that can describe complex logic controls with clean and concise source code. It has a multi-level design description function, layer-by-layer refinement, and finally can directly generate circuit-level descriptions. VHDL supports the design of synchronous, asynchronous, and random circuits that are unmatched by other hardware description languages. VHDL also supports a variety of design methods, supporting both bottom-up and top-down design; both modular and hierarchical.

Since VHDL has become the hardware description language standardized by the IEEE standard, most EDA tools support VHDL, which lays the foundation for the further promotion and wide application of VHDL. In the hardware circuit design process, the main design file is the source code written in VHDL. Because VHDL is easy to read and structure, it is easy to modify the design.

VHDL has a multi-level design description function that can describe both system-level circuits and gate-level circuits. The description can be either behavioral description, register transfer description or structure description, or a mixed-level description of the three. In addition, VHDL supports inertia delay and transmission delay, and can also accurately build hardware circuit models. VHDL supports pre-defined and custom data types, giving the hardware description a greater degree of freedom, allowing designers to easily create high-level system models.

When designers design with VHDL, they can concentrate on design optimization without first considering the choice of the device to be designed. When the design description is complete, a number of different device structures can be used to implement its function.

VHDL is a standardized hardware description language, and the same design description can be supported by different tools, making the porting of design description possible.

VHDL uses a library-based design approach to build a variety of reusable modules. These modules can be pre-designed or used in the archive modules of the previous design. These modules can be stored in the library and reused in future designs. The design results can be exchanged and shared among designers, reducing hardware circuits. design.

(1) Compared with other hardware description languages, VHDL has stronger behavior description ability, which determines that he is the best hardware description language in the system design field. Powerful behavioral description capabilities are important guarantees for avoiding specific device structures and describing and designing large-scale electronic systems from logical behavior.

(2) VHDL's rich simulation statements and library functions make it possible to check the functional feasibility of the design system in the early stage of any large system design, and to simulate the design at any time.

(3) The behavior description ability and program structure of the VHDL statement determine that he has the decomposition of supporting large-scale design and the reuse function of existing design. A large-scale system that meets market demands is efficient, and high-speed completion must be achieved by multiple people or even multiple development teams working together in parallel.

(4) For a certain design completed with VHDL, the EDA tool can be used for logic synthesis and optimization, and the VHDL description design is automatically converted into a gate-level netlist.

(5) VHDL has a relatively independent description of the design. The designer can design the independent device without understanding the structure of the hardware or managing the target device of the final design.

LIBRARY ieee;

USE ieee.std_logic_1164.all;

ENTITY shifter IS

PORT (

Data_in : IN STD_LOGIC_VECTOR(7 DOWNTO 0); --Entered data

n : IN STD_LOGIC_VECTOR(2 DOWNTO 0); --The number of shifts

Dir : IN STD_LOGIC; -- Direction of movement 0: Left 1: Right

Kind : IN STD_LOGIC_VECTOR(1 DOWNTO 0); --Moving type 00: Arithmetic shift 01: Logical shift 10: Loop shift

Clock : IN BIT; -- manual clock PULSE

Data_out : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) -- The result of the shift

);

END shifter;

ARCHITECTURE behav of shifter IS

BEGIN

PROCESS (data_in, n, dir, kind)

VARIABLE x,y : STD_LOGIC_VECTOR(7 DOWNTO 0);

VARIABLE ctrl0, ctrl1, ctrl2 : STD_LOGIC_VECTOR (3 DOWNTO 0);

BEGIN

IF (clock'EVENT AND clock = '1')THEN

- Generate control vector ctrl

Ctrl0 := n(0) & dir & kind(1) & kind(0);

Ctrl1 := n(1) & dir & kind(1) & kind(0);

Ctrl2 := n(2) & dir & kind(1) & kind(0);

CASE ctrl0 IS

WHEN “0000” | “0001” | “0010” | “0100” | “0101” | “0110” = “ x := data_in; --n=0 does not move

WHEN "1000" = " x := data_in(6 DOWNTO 0) & data_in(0); -- arithmetic left shift 1 bit

WHEN "1001" = " x := data_in(6 DOWNTO 0) & '0'; -- logically shifted 1 bit to the left

WHEN "1010" = " x := data_in(6 DOWNTO 0) & data_in(7); -- Cycle left 1 bit

WHEN "1100" = " x := data_in(7) & data_in(7 DOWNTO 1); --Arithmetic shift 1 bit to the right

WHEN "1101" = " x := '0' & data_in(7 DOWNTO 1); -- logically shifted 1 bit to the right

WHEN "1110" = " x := data_in(0) & data_in(7 DOWNTO 1); -- Loop right shift 1 bit

WHEN others = " null;

END CASE;

CASE ctrl1 IS

WHEN “0000” | “0001” | “0010” | “0100” | “0101” | “0110” = “ y := x; --n=0 does not move

WHEN "1000" = " y := x(5 DOWNTO 0) & x(0) & x(0); --Arithmetic shift left 2 bits

WHEN "1001" = " y := x(5 DOWNTO 0) & "00"; -- logically shifted 2 bits to the left

WHEN "1010" = " y := x(5 DOWNTO 0) & x(7 DOWNTO 6); -- Cycle left 2 bits

WHEN "1100" = " y := x(7) & x(7) & x(7 DOWNTO 2); --Arithmetic shift 2 bits to the right

WHEN "1101" = " y := "00" & x(7 DOWNTO 2); -- logically shift 2 bits to the right

WHEN "1110" = " y := x(1 DOWNTO 0) & x(7 DOWNTO 2); --Rotate right 2 bits

WHEN others = " null;

END CASE;

CASE ctrl2 IS

WHEN "0000" | "0001" | "0010" | "0100" | "0101" | "0110" = " data_out "= y; --n=0 does not move

WHEN "1000" = "data_out" = y(3 DOWNTO 0) & y(0) & y(0) & y(0) & y(0); --Arithmetic left shift

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