This article refers to the address: http:// Key words: CMOS image sensor; OV9120; image acquisition 1 Overview With the development of CMOS technology and the increasing market demand, CMOS image sensors have been rapidly developed. CMOS image sensor has the advantages of high integration, low cost, low power consumption, single working voltage, local pixel programmable, random reading, etc. It is suitable for ultra-miniature digital cameras, portable videophones, PC computer eyes, and video doorbells. , scanners, cameras, security surveillance, car security, machine vision, car phone, fingerprint recognition, mobile phones and other image areas. This article introduces the OV9120 black and white CMOS image sensor produced by OmniVision Technologies of the United States. It uses unique sensor patented process technology and advanced algorithms to solve the limitations of fixed image noise (FPN) of previous CMOS sensors. Therefore, it can be widely used in digital still camera, video conferencing, video telephony, computer vision, biometrics and the like. The OV9120 is available in a 48-pin LCC package with pinouts as shown in Figure 1. 3.1 Internal structure OV9120 built-in 1312 × 1036 resolution mirror array, 10-bit A / D converter, adjustable video window, SCCE interface, programmable frame rate control, programmable / automatic exposure gain control, internal and external frame synchronization, brightness equalization counter, digital Circuits such as video port, timing generator, black level calibration, and white balance control. Its internal structure is shown in Figure 2. 3.2 Performance characteristics The OV9120 is a 1.35 megapixel (1312×1036), 1/2-inch CMOS image sensor chip. It uses SXGA/VGA format and has a maximum frame rate of 30 frames per s (VGA). The chip uses CMOS optical sensing cores. The peripheral auxiliary circuits are integrated together with programmable control functions. The basic parameters of the OV9120 chip are as follows? ◠Image size: 6.66mm × 5.32mm, pixel size, 5.2μm × 5.2μm; ◠Signal to noise ratio > 54dB; ◠Gain adjustment range: 0 ~ 24dB; ◠When SXGA is output, the array size is 1280×1024, and when the VGA output is output, the array size is 640×480. ◠The power supply voltage is 3.3V and 2.5V DC; ◠Dark current: 28mV / s; ◠Dynamic range: 60dB. 3.3 Working principle The design of the CMOS mirror array is primarily based on a progressively transmitted field readout system and an electronic shutter with synchronized pixel readout circuitry. The electronic exposure control algorithm (or system rule) is based on the brightness of the entire image. When the scene (or scene) is normal, the general exposure is ideal. However, when the scene light is not suitable, the automatic exposure control (AEC) white/black ratio adjustment should be used to meet the application requirements. For VGA format output, the OV9120 image sensor has a window size ranging from 2×2 to 640×480, while for SXGA format output, the window range is from 2×4 to 1280×1024, and can be within the internal 1312×1036 boundary. Position anywhere. Changing the window size or position does not change the frame rate (or data rate). The frame rate can be changed by the main clock down, the vertical sync timing, or the QVGA format using the skip technology. The OV9120 has a 10-bit A/D converter embedded in it, so it can simultaneously output a 10-bit digital video stream D[9. . 0]. While outputting the digital video stream, a pixel synchronous clock PCLK, a horizontal reference signal HREF, and a vertical synchronization signal VSYNC may also be provided to facilitate reading of an image by an external circuit. When the RESET pin of the OV9120 is pulled high to VCC, all hardware will be reset. At the same time, the OV9120 will clear all registers and reset them to their default values. In fact, it is also possible to implement a reset by triggering on the SCCB interface. Since the SCCE port has access to all internal registers, the internal configuration of the OV9120 can be done through the SCCE serial control port. The SCCB interface has three leads: SCCE, SIO_C, and SIO_D. SCCE is the serial bus enable signal, SIO_C is the serial bus clock signal, and SIO_D is the serial bus data signal. SCCB's control of the bus function is completely realized by the state of the level on the three buses of SCCE, SIO_C, SIO_D and the mutual cooperation between the three. The conditions specified by the control bus are as follows: When SCCE changes from high to low, data transfer begins. When SCCE transitions from low to high, the data transfer ends. To avoid transmitting unwanted bits of information, SIO_D can be set high before the transfer begins and after the transfer ends, respectively. During data transfer, SCCE is always low, and the data transfer on SIO_D is controlled by SIO_C. When SIO_C is low, the data on SIO_D is valid and SIO_D is in a stable data state. Whenever a positive pulse occurs on SIO_C, the system will transmit one bit of data. The OV9120 has two modes of operation: master mode and slave mode. In the main mode, the OV9120 acts as the master device. At this time, the external crystal oscillator input on XCLK passes through the internal partial frequency to obtain the PCLK signal. When the OV9120 captures the image, the system can sequentially output the pixel value when the falling edge of PCLK arrives. At this time, the external is only the passive receiving signal. In the slave mode, the OV9120 can be used as a slave device. At this time, XCLK cannot be connected to the external crystal oscillator, but can be controlled by an external device, that is, the signal of the master device. That is, an MCLK clock signal is sent by the master device, and the pixel values ​​are sequentially transmitted under the synchronization of the signal. The whole image acquisition system is mainly composed of OV9120 image sensor chip, CPLD control module, RAM memory, DSP signal processor, crystal oscillator circuit and so on. In this system, the OV9120 is used as the image sensor of the system. First, the acquired image samples are quantized internally, and then the digital image is output under the control of external logic and stored in the image memory. As the main control module of the core control logic of the acquisition system, CPLD can be used to coordinate the work of other modules. The SCCB bus parameter configuration of the OV9120 is the starting point for the execution of the entire control logic module. Only after the OV9120 is configured with the SCCB bus can the image acquisition work be performed. The image data acquired by the OV9120 can be stored in the SRAM for use by the DSP to complete the interaction between the image acquisition system and the DSP recognition system. The schematic diagram of the system is shown in Figure 3. After the system is powered on, the CMOS image acquisition chip should be initialized first to determine the window opening position, window size, and black and white working mode of the captured image. These parameters are controlled by the corresponding register values ​​within the OV9120. Since the value of the internal register can be accessed through the SCCB serial control bus interface provided on the OV9120 chip, the CPLD can configure the parameters by controlling the SCCB bus. The specific method of configuration can adopt the method of three-phase write data, that is, the ID address of the OV9120 is first sent in the process of writing the register, and then the destination register address of the write data is sent, followed by the data to be written. If the data is written to the register continuously, then after writing a register, the OV9120 will automatically increment the register address and continue writing down under program control without re-entering the address. After the system is configured, image data will be collected. In the process of acquiring an image, the most important thing is to discriminate the start and end times of one frame of image data. After carefully studying the OV9120 output synchronization signal (VSYNC is the vertical synchronization signal, HREF is the horizontal synchronization signal, PCLK is the output data synchronization signal), the VHDL language can be used to achieve precise control of the starting point of the acquisition process. The rising edge of VSYNC indicates the arrival of a new frame of image, and the falling edge indicates the start of image acquisition of one frame (the CMOS image sensor captures the image in columns). HREF is a horizontal sync signal whose rising edge indicates the start of a column of image data. PCLK is the output data sync signal. HREF is high to start effective data acquisition, and the falling edge of PCLK indicates the generation of data. Each time a falling edge of PCLK occurs, the system transmits one bit of data. During HREF high, the system transmits a total of 1280 bits of data. That is to say: HREF will appear 1024 times high in one frame of image, that is, when VSYNC is low. The arrival of the rising edge of the next VSYNC signal indicates the end of the image acquisition process with a resolution of 1280 x 1024. The software design for acquisition is implemented in the MAX+plusII environment. The main job of software design is the configuration of the OV9120 by CPLD. At the beginning of charging, the system is first initialized. The global clock of the CPLD can be generated by a 24MHz crystal oscillator circuit. Configure SCCB first in the configuration. After the configuration is complete, set SCCE to 1. After receiving the start acquisition signal of the DSP, it is determined whether to start collecting data according to the state of the synchronization signal, and the data can be sent to the SRAM while collecting data. When the DSP receives the read signal of the CPLD, it can start reading the data and complete the image processing in the DSP. The main program of the acquisition process is as follows: Reset2:process(reset_i,n1,clk) Begin If reset_i='0'then scce_p<='1'; Else If(n1='1' or m1='1')then Scce_p<='1'; Else scce p<='0'; End if; End if; End process reset2; Clk1: process(n1,clk) Variable a: integer range 254 to 0; Begin If(sio_c_start='0' OR n1='1') then q<='1'; a:=0; Else If(clk'event and clk='1') then If(sio_c start='1' and n1='0') then If a<254 then; a:=a+1; Else a:=1; End if; If a<127 then q<='0'; Else q<='1'; end if; End if; End if; End if; End process clk1; Lock:process(sio_c_start,q) Variable n: integer range 8 to 0; Begin If( sio_c_start='0' then load<='1';n:=0; Else If (q 'event and q='0') then If n<8 then n?=n+1; Load<='0'; Else n:=0;load<='1'; End if; End if; End if; End process lock; Reg1: process(n1,q,load) Variable pp:std_logic_vector(7 downto 0);? Variable b: integer range 7 to 0; Variable c: integer range 13 to 0; Begin If(n1='1'or reset_i='0') then p<='1';c:=0; b:=0;QB<='0'; Else If(q'event and q='0')then If load='1' then; c:=c+1? If c<13 then If c=1 then Pp:="11000010"; Elsif c=2 then Pp:="00001100"; Elsif c=3 then Pp:="00101001"; Elsif c=4 then Pp?="11000010"; Elsif c=5 then Pp:="00001101"; Elsif c=6 then Pp:="10000000"; Elsif c=7 then Pp:="11000010"; Elsif c=8 then Pp:="00010001"; Elsif c=9 then Pp:="10000000"; Elsif c=10 then Pp:="11000010"; Elsif c=11 then Pp:="00010011"; Elsif c=12 then Pp:="00010111"? End if; b:=0; p<=pp(7); Elsif c=13 then p<='0'; QB<='1'; End if; Else If b<7 then b:=b+1; Pp(7 downto 1):=pp(6 ownto 0);? p<=pp(7);? Else p<='1'; End if; End if; End if; End if; End process reg1; Fancy Usb Flash Drive,Pvc Usb Stick With Logo,Stock Usb Flash Drive,Usb Flash Drive Features,custom PVC USB flash drive Shenzhen Konchang Electronic Technology Co.,Ltd , https://www.konchangs.com
2 pin function
3 structural performance and working principle
   The ZV port is the focus adjustment video port of the camera (lens). The ZV function of the OV9120 allows the camera lens to zoom and move toward (or away from) the target. The OV9120 can set the exposure time using an external master device. When FREX is set to 1, the pixel array is quickly charged and the sensor remains high to capture an image (or object). When FREX transitions to 0, the video stream is delivered to the output port in a progressive read mode. When data is output from the OV9120 video output, special care should be taken to prevent image array exposure from affecting the integrity of the captured image data. An automatic shutter synchronized with the screen exposure rate minimizes this effect.
4 OV9120 application in image acquisition system The three-phase write data becomes two-phase write data. Since the system only needs to change the data of a limited number of discontinuous registers, it is a waste of time and resources to configure all the registers, so it is possible to write data only to the registers that need to change the data. For each changed register, a three-phase write data method is used.