The risk of microelectronic circuits is greater than ever, and the chief culprit is electrostatic discharge (ESD). These scourges are secret killers and are particularly vulnerable to attacking sensitive ICs. A single electrostatic discharge event can send the PCB to hell. As long as you miss a step in antistatic discharge design, it may mean delays in time to market, impact on development progress, and angering customers. Under certain high pressure conditions, it even means that your rice bowl is not guaranteed.
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In the ever-shrinking microelectronics era, ESD events are likely to ruin your product if ESD transients don't actively stop them before they appear on the PCB traces.
At the time of this writing, I just remembered something quite interesting that happened a few months ago. A customer who is going crazy has contacted us for emergency help, hoping to protect his system from "angry" ESD transients. The poor guy suffered a series of anti-ESD failures and made his product plan full of soup. He must have missed some steps.
First, he did not implement a protection clamp circuit at any I/O interface, nor did he place a PCB pad for the TVS clamp device as a "safety valve" measure he needed to protect. To complicate matters further, the I/O ports on this particular product are connected to some high-speed and very sensitive communication ICs. The lack of much ESD has caused communication failures on these boards. Figure 1 shows an example of using a clamp diode on a data line. 
Figure 1: TVS diodes provide ESD protection on the data line. This example shows a USB 2.0 data cable with ESD protection.
Version 1 and Version 2 will also be released when the first board fails the ESD compliance test. This time it is no longer "瞎 guessed." The customer apparently found a transient voltage suppression (TVS) clamp tube with an ESD rated voltage of ±15kV. He placed some TVS on some of the board's I/O ports and was quite happy to see that the device would guarantee an ESD strike of ±15kV. Although the direction of this step is correct, he still fundamentally misunderstood the ESD threat. The second version of the circuit still did not pass the ±15kV voltage test, although at this time he found a certain degree of improvement with TVS. Figure 2 shows how the TVS diode "clamps" the voltage from the ESD pulse. 
Figure 2: Clamping diodes reduce the voltage from the ESL pulse and thus protect your circuit from damage.
Transient Environment: Transient environment
Transient voltage: Transient voltage
Transient current: Transient current
Clamped voltage: Clamped voltage
TVS Diode: TVS Diode
Data Line Transceiver IC: Data Line Transceiver IC
The engineer turned to us with horror as a result of two electric shocks. With our in-depth analysis of the problem, I really feel the anxiety and fear of this engineer. In fact, I have a deep feeling that the ESD transient signal on the engineer's PCB trace will not only endanger the communication device on the board, but it is no exaggeration to threaten his work. He has long needed a solution. Since time is not waiting, and there is another customer on the other end of the design that has been postponed, we have to take care of this problem. He sent the board to our Semtech lab, hoping that we would protect this product from ESD and protect its credibility and work.
However, the first misunderstanding we need to clarify is that the ±15kV rating on the TVS Clamp Device Data Sheet has little to do with the system-level protection thresholds he wants to achieve on the PCB. That rating relates to the fault threshold of the TVS device itself, but it is not equivalent to the degree of immunity that the system has to guarantee. As the facts show, his system circuitry is too sensitive, and it is difficult to achieve system-level immunity to ±15kV while meeting the capacitive constraints and size requirements for TVS devices.
In addition, I want to explain that not all TVS devices are born the same. The clamping performance of two TVS clamp devices from different manufacturers can vary widely. If the product development cycle is very tight, choosing a cheap, cottage TVS device is not a good strategy. Therefore, we have modified his board with some newer high-performance low-side clamps that can suppress very high peak currents. In this way, the anti-interference performance of this board has been significantly improved, as shown in the following figure. 
Figure 3: Increasing transient voltage suppression can significantly reduce the clamping voltage and protect sensitive ICs.
Voltage: Voltage
TVS Clamping Response (+8kV Contact Discharge): TVS Clamp Response (+8kV Contact Discharge)
+8kV Contact voltage waveform: +8kV contact voltage waveform
No external TVS protection implemented: No external TVS protection
Clamped ESD voltage (+8kV contact) with Semtech RClamp0531TQ TVS: Clamped ESD voltage (+8kV contact voltage) using Semtech RClamp0531TQ TVS
Time: Time
His system can now be easily tested with ±8kV (±8kV is sufficient in most cases). The board still failed to pass the ±15kV contact discharge test (expansion target), but it was much better than the previous results. On this basis, in order to further improve the robustness of the system, we added a small series resistor on the line, which is enough to suppress the residual transient current, but not enough to affect the signal performance.
While increasing resistance is not the ideal solution, it does improve ESD performance, and in the later stages of such a design, it provides a relatively easy to implement fix. The end result shows that everything is fine: a robust product, a delightful end user, a happy boss, and an engineer who has a deeper understanding of ESD protection knowledge. As they say, "increasing the resistance has the effect of four or two pounds." I guess in his next design, our friends will be more proactive in avoiding any ESD mistakes that will be discovered at the last moment.
About the Author:
Timothy Puls is a product marketing engineer at Semtech.
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