Surprising and sometimes confusing series of wireless standards, with different frequencies, bandwidths, protocols, and formats, provide users with unprecedented connectivity and accessibility. But at the same time, it also means that wireless system engineers face severe challenges in designing or investigating problems, performance, and options. The solution seems to be clear: reduce the use of dedicated hardware as much as possible and replace it with software-defined radio (SDR) schemes in order to implement and manage as many sending and receiving functions as possible. The current market for high-performance, low-power processors (including FPGAs) and their ability to execute complex algorithms at high speeds enables such real-time solutions. However, this solution has a real obstacle: It is difficult to design a wideband analog circuit for the receiver and transmitter signal paths. Therefore, most broadband SDRs use a set of overlapping, parallel analog channels. Each channel is optimized for a particular segment within the overall band, and the bandwidth within each segment matches the target signal. Although this method is technically feasible, the hardware, PC board area, and power consumption required to implement this technology are all quite significant - and of course there are costs. This is where Epiq SoluTIons (Schaumburg, Ill.) developed its latest SDR unit, the Maveriq multi-channel reconfigurable RF transceiver (see Figure 1). The transceiver is a built-in solid state drive (SSD) that combines multiple RF transceivers for data logging, an Intel x86 CPU running on Linux, and an advanced platform for Gigabit Ethernet interfaces for high-speed data access. . It provides excellent SDR capability in a small package and covers the 100MHz to 6GHz tuning range. As a designer and builder of advanced, reconfigurable radio systems for mission-critical applications, the company's goal is to provide a more powerful multi-channel version than the existing MatchsTIq SDR. Figure 1: Maveriq multi-channel reconfigurable RF transceiver. Despite its advanced features and capabilities, Maveriq is a portable low-power platform, and previous solutions required a lot of heavy hardware configuration. Maveriq combines a library of ready-to-run professional software applications that can be used immediately to solve difficult signal processing requirements. These requirements include: scanning and decoding cellular radio signals from base stations and mobile phones; recording broadband RF and RF playback signals on internal hard disks (SSDs); and implementing 2<2>Multiple Input Multiple Output (MIMO) waveforms. The new IC tailored for SDR applications—ADI's AD9361 RF Agile Transceiver—allows Epiq engineers to package so many functions in a small, low-power unit. John Orlando, Epiq’s CEO and System Architect, said: “The AD9361 provides us with the RF flexibility and integration required for the next-generation SDR platform.†This 10mm&Times10mm chip-scale device integrates dual independent channels (as shown in Figure 2) with user tunable bandwidth from 200kHz to 56MHz, and a 12-bit ADC and DAC operating at up to 61.44MSPS, plus an additional 70MHz to 6GHz Additional characteristics and performance required for the signal chain. Users can adjust key operating parameters in real time to match application requirements as closely as possible. Using this device can reduce the overall size of the entire analog front end (AFE), while keeping the power consumption of this part of the design within 1W range, which is kept within the product power budget. Figure 2: Analog Devices AD9361 RF Agile Transceiver IC Block Diagram. The entire Maveriq unit (shown in Figure 3) uses a pair of AD9361s to support 2x2 MIMO or 4-channel receiver configurations. The RF tuning range is 100MHz to 6GHz, the step size is 1kHz, and the tuning time is 2ms. The unit includes an integrated GPS receiver with 1PPS performance, an internal SSD that supports data recording rates of 100MB/s or more, a capacity of up to 1TB, and Gigabit Ethernet that interfaces with external systems. Figure 3: Maveriq unit simplified system block diagram Processing capabilities are centered on dual-core Intel x86 CPUs running Linux and FPGAs for signal processing tasks, along with real-time loadable/executable software applications, all supported by application-specific software development kits (SDKs). The overall cell size is only 9.1" x 6.6" x 1.7" (23cm x 16.7cm x 4.3cm), weighs 1.9lb (0.9kg), and consumes 15W (depending on FPGA and I/O usage). Of course, proper RF performance can give full play to processing capabilities. The receiver's typical noise figure is less than 8dB, and typical IIP3 is –10dBm. The sender performance parameters (such as bandwidth, tuning and speed) can compensate for the number of receivers and the output power consumption is +5 dBm. Although the AD9361 IC is the key to achieving this design, it can always achieve further performance improvements. Some applications require the RF performance to be scaled down to 20 MHz and below, which is beyond the AD9361's ability to handle. In addition, the choice of RF components that can operate at as low as 20MHz (such as low noise amplifiers, LNAs) is equally difficult, especially in size and power-constrained designs. In general, one would expect that the advancements in low-power processing technology combined with large-capacity memory products, coupled with high-speed digital I/O and connectivity (all motivated by Moore's Law), are sufficient for small, high-performance SDRs. In fact, the front-end channels used for the receive path and the transmit path are of equal importance, and the development of RF ICs that combine analog processing, filtering, and conversion not only minimizes the burden on the algorithm, but also achieves most of the The actual performance of SDR.
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