Abstract: MPC860 is a PowerPC series product. PowerPC can be used in a variety of operating environments. It is widely used in portable devices to servers. The TMS320C6000 series is a DSP chip introduced by TI in 1997. This chip is a fixed-point, floating-point compatible DSP series. They provide the HPI (Host Port Inter face) interface, which describes the hardware design of the HPI interface between the TMS320C6000 and the MPC860. It has been verified by experiments that the MPC860 can read or write to the expansion bus, and the design has already achieved preliminary functions. Therefore, it has certain practicability. 1 Main features of TMS320C6000 The TMS320C6000 series of DSPs (Digital Signal Processors) is TI's latest parallel processing digital signal processor. There are 8 parallel processing units in the TMS320C6000. Divided into the same two groups. Its architecture uses a very long instruction word (VLIW) structure with a single instruction word length of 32 bits. Eight instructions form an instruction package. The total word length is 8 & TImes; 32 = 256 bit. The chip has a dedicated instruction allocation module internally, which can allocate 256-bit instruction packets to 8 processing units at the same time and run simultaneously by 8 units. The chip's maximum clock frequency can reach 300MHz, which is obtained by multiplying the input clock by an on-chip phase-locked loop (PLL). When the 8 processing units in the chip are simultaneously running. The maximum processing capacity can reach 2400 MIPS. 2 TMS320C6000 expansion bus Currently, only the C6202 and C6203 in the TMS320C6000 series have an expansion bus. They are based on the C6201/C6701 host interface (HPI). The expansion bus can be divided into two parts in terms of structure: I/O interface and host interface, as shown in Figure 1. The expansion bus is a 32-bit wide bus that supports interfaces to asynchronous peripherals, asynchronous/synchronous FIFOs, PCI bridges, and external host processors. It also provides a flexible bus arbitration mechanism that can be used for internal arbitration or external logic. I/O interface, the expansion bus has a total of four XCE external spaces, and four spaces can be configured into two working modes: asynchronous I/O mode and synchronous FIFO mode. These two modes can work simultaneously in one system. The interface signal timing of the asynchronous I/O mode is similar to that of EMIF, and has a high degree of programmability. In this mode, the four address signals of the expansion bus interface enable up to 16 external devices to be attached to each XCE space. The FIFO mode provides the ability to interface seamlessly with the synchronous FIFO, allowing direct control of one synchronous FIFO for read operations or four simultaneous FIFOs for write operations. With a small amount of external logic, each XCE space can manage 16 read operations FIFOs or 16 write operation FIFOs. The expansion bus I/O port is connected to the other memory space of the DSP by the DMA controller. The host interface also has two modes of operation: synchronous and asynchronous. The synchronous mode provides both master and slave modes of operation, in which case the address signal and the data signal are multiplexed with the same pin. Asynchronous mode has only subordinate function, which is completely similar to the HPI operation of C6201/C6211/C6701/C6711, except that the data width is 32bit. Asynchronous mode can be used to interface with other microprocessors. The connection of the expansion bus host interface to the DSP memory is done by the DMA auxiliary channel. In synchronous host interface mode, the host's data is multiplexed with the address signals and is compatible with the i960Jx. At present, the mainstream PCI interface chip adopts the i960 bus as the internal bus of the chip, so that the external logic required by the C6000 and the PCI bus can be minimized. Especially when acting as a slave processor, the synchronous host interface can also be easily interfaced with other general purpose processors. The C6202's expansion bus also has the ability to transmit bursts. This article uses this way to achieve the interface between the MPC860 and C6202 expansion bus. The operating frequency of the C6202 processor can be up to 50MHz, and it can be up to 200MHz after 4 times internal frequency. Up to 8 instructions can be executed in parallel in each clock cycle, which can achieve 1600MIPS fixed-point computing capability. The time to complete 1024-point fixed-point FFT is only It takes 70μs. 3 MPC860 Introduction The MPC860 is Motorola's monolithic integrated embedded microprocessor that integrates peripheral components commonly used in microprocessors and communications, making it ideal for the Internet and data communications markets. The MPC860 communication processor can provide 2~4 serial communication controllers, different specifications of instructions and data cache, and various levels of network protocol support according to user requirements. The product is designed for broadband access devices such as remote access routers, DSLAMs, access hubs, LAN/WAN switches, PBX systems and gateways. The MPC860 includes three main modules: Power PC Core, System Interface Unit (SIU), and Communication Processing Module (CPM). PowerPC is the primary processor unit, commonly referred to as the Embedded Power PC core (or EPPC), which includes a cache and memory management unit (MMU) with 50 MIPS instruction speed at 40 MHz clock; the second major module is The system interface unit, whose main function is to provide an interface between the internal bus and the external bus; the third main module is the communication processor module, and the CPM transmits and receives data communication on different communication devices such as SCC and SMC, and the communication device can work independently. . 4 expansion bus interface implementation The MPC860 integrates an embedded PowerPC core and a Communication Processing Module (CPM) using a specific RISC processor. This dual processor architecture is superior to traditional architectures because CPM can offload peripheral tasks from the embedded PowerPC core. 4.1 Interface Implementation In the synchronous host interface mode, the interfaces of the C6202 and MPC860 are shown in Figure 2. Although the C6202 in Figure 2 is in slave mode, it has the ability to extend bus arbitration for the FIFO interface of asynchronous I/O and expansion buses. The arbitration within the MPC860 is used only when the two devices share the bus.
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