Photovoltaic power stations use a large number of photovoltaic panels to complete the conversion from light energy to DC power, and then use inverters to convert the DC power to 50 Hz AC power and transmit it to the grid. There is a huge demand for power control and conversion equipment in the entire photovoltaic power station. The communication management machine is the equipment that connects the various equipment in the power station to the power station central console. Through the control platform, it controls the downstream Rtu equipment to realize the collection of information such as remote signaling, telemetry, and remote control, and feedback the message to the dispatch center, and then the control center administrator Through the processing and analysis of the message, the command to be executed is selected to achieve the goal of telecontrol output scheduling command. At present, there are mainly three widely used communication management machine implementation schemes: PowerPC processor + serial port expansion chip architecture, ARM processor architecture, and ARM processor + FPGA architecture. Among them: (1) PowerPC processor + serial port expansion chip architecture uses PowerPC processor with communication coprocessor as the core of the system, and uses serial communication expansion chip to expand up to 16 serial ports for PowerPC. All data processing and calculations are completed by the PowerPC processor. When all the serial ports are used, the entire system runs slowly, and the real-time performance of the data is difficult to guarantee. (2) The communication management machine implemented by using a separate ARM processor as the core has a simple structure, but the number of serial ports that can be supported is limited by the number of serial ports integrated by the ARM processor itself, and generally does not exceed 6, which cannot meet the requirements of the mass equipment in photovoltaic power plants. demand. (3) ARM processor + FPGA architecture uses FPGA to complete serial port expansion, and based on ARM processor to complete data processing and network protocol realization, it is essentially the same as the solution based on PowerPC + serial port expansion chip. This scheme increases the complexity of the system, but the single performance improvement is not obvious. The problem with the above three solutions is that the system has one and only one core unit. Once the system goes down, the system has to be restarted. If the system is not restored, the entire system is completely disconnected from the power station center console. , Unable to receive control commands from the center console. Based on Intel’s new SoC FPGA chip, this paper uses a single SoC FPGA chip to implement the system originally implemented with separate FPGA and ARM processors, and builds a redundant monitoring system on the FPGA. While improving the performance of the system, it ensures the online recoverability of the system. Intel Cyclone V SoC FPGA chip 5CSEMA4U23C6 is a SoC chip that integrates a high-performance dual-core ARM Cortex-A9 CPU and FPGA on a single chip. It is the core unit of the system. In this system, the FPGA part on the SoC FPGA chip is mainly responsible for the expansion of the UART interface and the acceleration of the MODBUS protocol. In the power system, almost all devices support the standard RS485 interface, and use the MODBUS protocol to communicate with other devices. In photovoltaic power plants, because of the large amount of equipment and the large amount of data, one RS485 port of the communication management machine can only communicate with one device at the same time, which leads to a bottleneck in the data transmission speed. In order to solve this problem, multiple MODBUS network ports are often used to realize the management of numerous devices [2]. After the data of many power equipment is collected by the communication management machine, it finally needs to interact with the central control background of the power station through the Ethernet interface. The data interaction is mainly realized through the IEC104 protocol, and the realization of the IEC104 protocol is processed by the hardware in the SoC FPGA The system (Hard Process System, HPS) runs a mature Linux operating system to complete. 2.1 SoC FPGA configuration circuit design In order to make the system support remote online upgrade, this system sets the FPGA part of the SoC FPGA to receive the configuration data of the HPS part. The HPS part can receive the FPGA configuration file transmitted by the serial port or the network port. When running, the HPS part of the SoC FPGA starts and runs the Linux operating system first, and the FPGA part is configured after the Linux operating system is started. If you need to update the FPGA configuration data remotely, you only need to transfer the new FPGA configuration content to the disk managed by the operating system through the network port to replace the original configuration file, and the new configuration file can be used when the system is started next time. FPGA. 2.2 SoC FPGA startup circuit design The HPS part of SoC FPGA runs Linux operating system, and HPS supports booting from SD card, QSPI Flash, and NAND Flash memory. NAND Flash and QSPI Flash memory are generally installed on the circuit board by soldering, while the SD card is detachable and can be read and written separately on the PC. In the industrial field, if the equipment system is damaged and the system needs to be re-programmed, the QSPI Flash and NAND Flash can only be programmed online by PC because they are soldered on the PCB, while the SD card can be pre-programmed with the system SD The card is replaced, thus saving the workload of on-site maintenance. 2.3 RS485 interface circuit design As an industrial device, the communication interface of the communication management machine may withstand various impacts, including strong common-mode voltage, high-voltage static electricity, lightning strikes, etc. Therefore, protective measures for the communication interface are very important. In this system, the RSM3485 module is used to complete the two-way conversion from TTL level to RS485 level. RSM3485 module realizes standard RS485 interface, with ESD protection, short circuit or open circuit failure protection function, built-in 120 kΩ pull-up and pull-down resistors, twisted pair output, providing ESD discharge function of ±4 kV in contact and ±8 kV in air discharge, At the same time, a lightning protection circuit is designed to prevent damage to the communication interface in the event of a lightning strike. The interface circuit diagram is shown in Figure 1. 2.4 Ethernet interface scheme design The communication management machine of the power system requires the provision of dual main and backup network ports to ensure that when one of the network ports fails, the other network port can continue to transmit necessary data. The 5CSEMA4U23C6 chip provides two Gigabit Ethernet MACs by default, but these two MACs are partly managed by HPS. In order to ensure the reliability of the network port, even when part of the ARM system is down, the backup network port can also be used. It works normally, only one MAC layer is used in the design, and is driven by HPS, and the other network port is implemented using the NIOS II soft core control integrated Ethernet communication chip W5500. The W5500 chip is a single-chip TCP/IP protocol chip implemented in full hardware, supports 8 Socket ports, and is very convenient and reliable to use. Use NIOS II to control W5500 to complete Ethernet transmission. Even if HPS works abnormally, the NIOS II CPU in FPGA can continue to send and receive data through W5500 to ensure the stable operation of the backup network port. Since SoC FPGA is an innovative architecture that integrates FPGA and high-performance HPS, it can make full use of the powerful data processing capabilities of HPS, flexible customization features on the FPGA side, and high-speed communication bridge between HPS and FPGA during design. Various tasks are reasonably allocated to FPGA or HPS according to their characteristics, and the two cooperate to achieve the highest performance. The FPGA side mainly implements the expansion of the UART communication interface and the backup system based on the NIOS II processor. The HPS end mainly realizes the conversion between a large amount of data processing and communication protocols. Figure 2 is a block diagram of the functional division on the SoC FPGA. 3.1 FPGA logic design The FPGA side logic part realizes 16 UART communication control units that support MODBUS frame automatic recognition, as shown in Figure 3. Each unit is composed of CRC check logic, serial data receiving and sending buffer, core control state machine and MODBUS frame recognition logic. Under the control of the core control state machine, each unit automatically completes the sending and receiving of MODBUS data frames and the generation of data check codes, and transmits the data received and sent by MODBUS with HPS via the Avalon MM Slave interface. Fig. 4 is the working state transition diagram of the enhanced UART communication control unit supporting MODBUS frame automatic recognition when receiving data. The whole state machine is composed of idle state (IDLE), receiving data state (GET_DATA), receiving timeout state (TIMEOUT), receiving byte data completion state (GET_BYTE), frame transmission completion state (FRAME_DONE). When the host sends a MODBUS request frame, the module enters the receiving data state (GET_DATA), and every time a byte is received, it jumps to the receiving byte completion state (GET_BYTE). When the frame end determination signal is valid, it indicates a frame of data When the reception is completed, it enters the frame receiving completion state. By comparing the CRC data field in the received data frame with the check data generated by the CRC check unit in the FPGA for the frame, it is determined whether the current frame is correct. Then send an interrupt request to HPS through the FPGA and HPS interconnection bridge, and report the verification result of the current frame. The Linux driver on the HPS side will complete the corresponding processing according to the verification result. If the verification is correct, read the frame data And submit it to the upper MODBUS protocol layer for further analysis and processing. If the frame is wrong, the frame is discarded and the error handling procedure is entered. 3.2 Linux software design The HPS in the SoC FPGA chip runs the Linux operating system, and runs the application program of the communication management machine on the Linux system. The application program mainly includes three parts, namely MODBUS protocol master station, IEC104 protocol slave station, protocol conversion program between MODBUS and IEC104 protocol. Among them, the MODBUS protocol master station runs the open source Libmodbus protocol stack to complete the sending and receiving of MODBUS instructions and data. Libmodbus protocol stack is a free and open source MODBUS protocol stack that supports MODBUS protocol master and slave functions. Because this system uses the hardware logic circuit on the FPGA side to have realized part of the functions of the MODBUS protocol, such as frame end judgment, CRC check, etc. Therefore, the Libmodbus protocol stack has been reduced and optimized to a certain extent, and the part of receiving and verifying the underlying data frame is removed, and only the instruction and data analysis part is used. This is also the advantage of this system. The bottom layer of the MODBUS protocol is realized through FPGA side hardware. The content reduces the workload of the processor and enables the processor to easily support up to 16 ports based on the MODBUS protocol. In order to facilitate the control of the 16-port MODBUS accelerator on the FPGA side, a separate process is set up on the Linux side for the control of the 16-port MODBUS accelerator. When the task is scheduled and the execution opportunity is obtained, the status of the current port will be inquired in turn. Then execute the corresponding processing code according to the obtained port status. The program flow is shown in Figure 5. Idle state: When the state of a port is queried as idle, it indicates that the port has correctly completed a round of data transmission and reception. Before the arrival of a new communication command, the port will be in an idle state, that is, there is no need to send data, nor Need to receive data, MODBUS port is in idle state. Receiving success: When a certain port has successfully received the returned data, it will start to process the received data, and after completion, enter the status query of the next port. Receiving timeout: When the query finds that a port does not respond within the set response time, it will return the receiving timeout status. If the timeout status is detected, the system starts to process the timeout. After the reception timeout process is completed, it enters the status query work of the next port. Receiving error: When an error in receiving data on a certain port is found, the receiving error processing will be performed. When the receiving error processing is completed, enter the status query work of the next port. The part of the task code framework is as follows: for(i=0;i《=15;i++) { port_state=mdp_state_read(port_num);//Read the specified port state switch (port_state) { case NO_STATE: break;//No ready port case RX_DONE: //Receive data successfully …//Received data processing code module break; case RX_TIMEOUT: //Receive timeout …//Receive timeout port processing code module break; case RX_ERROR://Receive error …//Receive error port processing code module break; default: printf("default %d", port_num);//The default is misread Mishandling, set the status register as an error flag FPGA_WR16 ((port_num《》8 | 128), 1); }//After reading the 16th port, go back to port 0 to read if (port_num == 15) port_num = 0; else port_num ++; //The port number adds 1 } usleep(30000); //Release CPU permissions 3.3 NIOS II backup system software design Normally, the NIOS II CPU is in the standby state. If the NIOS II CPU does not receive the status message within the set time, it indicates that the HPS system side software system has crashed. The NIOS II CPU then confirms the current status by the status indicator signal interconnected with the HPS The operating system is down or the application is abnormal. If the application is abnormal, the security monitoring software on the Linux side is triggered to restart the application; if the operating system is abnormal, the backup network port is activated to report the current system fault information to the power station center console, and the HPS is restarted through hardware reset. Figure 6 shows the program flow chart of the NIOS II backup system. Table 1 takes 16 RS485 ports, each port completes the data reading of the device on the bus every 500 ms, and the average length of each communication data frame is 64 B as an example, analyzes the system scheme (referred to as SoC FPGA) within 1 s Solution) and PowerPC+ serial port expansion chip ST16C2550 solution (PowerPC solution for short) in several aspects, such as the number of serial port chips, CPU CRC calculation transactions, CPU processing interruption times, and the independence of backup network ports. The photovoltaic power communication management machine system based on Intel SoC FPGA designed in this paper gives full play to the advantages of FPGA in processing multi-channel parallel data communication, greatly reduces the interrupt overhead of the embedded processor in the traditional solution when managing communication transactions, and The total number of RS485 ports supporting MODBUS protocol in a single system is increased, which can effectively simplify the layout and wiring of the communication network of photovoltaic power plants. At the same time, due to the programmable characteristics of FPGA, the system can be upgraded by reprogramming the FPGA without changing the hardware circuit, solving the problem of multiple devices and large data volume in photovoltaic power systems, and increasing the system The scope of application. Android Tablet C&Q Technology (Guangzhou) Co.,Ltd. , https://www.gzcqteq.com
Design of photovoltaic power communication management machine system based on Intel SoC FPGA
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