Abstract : The speed of data acquisition systems constrains the application of electrical capacitance tomography in high-speed equipment such as aerospace engine gas path monitoring systems. To this end, a new type of capacitor data acquisition system based on FPGA is designed, which uses DDR2 storage technology and PCI bus technology to achieve high-speed data transmission. At the same time, the Kalman filter is used instead of the traditional FIR filter, which effectively improves the filtering efficiency. The test results show that the system has the advantages of strong anti-interference ability, high sampling accuracy and fast processing speed. The engine structure of the aircraft is complex and the working environment is bad. Accurate and rapid detection has always been a major technical problem facing airlines. The exhaust gas discharged from the aeroengine is mainly a mixed multiphase fluid such as a large amount of exhaust gas, incomplete combustion droplets, and metal chips generated by mechanical wear. By detecting and analyzing the characteristics of these particles, it is possible to reflect the working state of the engine in real time and provide a basis for the engine to be repaired as appropriate. ECT (Electrical Capacitance Tomog-raphy) has the advantages of non-intrusion, visualization and fast response, which makes it have a significant advantage in the detection of low-speed multiphase fluid process parameters. At present, there are reports on the application of ECT system in the detection of dilute phase pulverized coal gas-solid two-phase flow. The related literature does not report the ECT system's report on the special gas-solid two-phase flow detection of high-temperature, high-speed aero-engine exhaust. Data acquisition speed is one of the bottlenecks restricting the ECT system in aviation engine exhaust gas detection applications. In response to this problem, this paper designs a new high-speed data acquisition system that significantly improves the speed of data acquisition while ensuring a certain accuracy. It mainly includes the following two aspects of work: Figure 1 shows the structure of the ECT system. It consists of three parts: an array capacitive sensor, a data acquisition and signal processing unit, and an image reconstruction and analysis display unit. The overall design block diagram of the aero engine air circuit detection system based on ECT is shown in Figure 2. The system uses two FPGA chips as the core processor. One of them uses Xilinx's Spartan-6 series XC6SLX16-2CSG324 to control the 12-bit high-speed analog-to-digital converter AD9224 to directly sample the C/V conversion circuit output Vo() and store the A/D converted signal to DDR2. in. The other chip selects Altera's CycloneJl series EP2C5Q208C8N chip to realize the filtering and phase sensitive demodulation of the stored data, and transmits the processed data to the host computer through the PCI bus in DMA mode to complete the image reconstruction. The data acquisition system is mainly composed of three parts: A/D conversion, signal processing and PCI bus data transmission. 2.1 A/D conversion design Because the signal collected by the ECT system is weak, the accuracy of the A/D conversion circuit will directly affect the imaging effect. This system uses the high-speed chip AD9224 of American Analog Devices. The AD9224 has a 12-bit bit width and a 40 MS/s slew rate. The input range of the AD9224 is controlled by a reference terminal that supports DC or AC-coupled single-ended or differential inputs. The system excitation frequency used in this paper is 500 kHz and the data is collected in a serial manner. Therefore, the AC-coupled single-ended input mode is selected, as shown in Figure 3. In order to obtain a wider input range (2X 唧), the external reference voltage is biased to 2V, and the op amp's input range is from 2V to +2V. The operation in the circuit plays two roles: one is to 2.2 Data Processing Module Design In order to achieve fast data storage, a Micron 128 MB DDR2 SDRAM chip was used in the system. Figure 4 shows the conversion structure of the state machine when the DDR2 memory is operating. After the system initialization is completed, the state machine enters the IDLE state. Then according to different request instructions, the state machine switches to the corresponding state, and sends the instruction to the DDR2 memory chip, and triggers the counter to start counting. When the specified time interval is met, the controller can accept the new instruction again and convert to the corresponding working state according to the request. 2.3 Data Transmission Module Design This system uses the dedicated PCI interface chip PCI9054 to realize data transmission, and converts the complex PCI bus interface into a simple I/O interface. In terms of data stream transmission, the board uses memory space and uses DMA for high-speed data transmission [61]. Figure 5 shows the structure of the PCI9054 when performing target DMA reading and writing. After the host or FPGA only needs to issue the DMA start signal, all operations of the DMA can be completed by the PCI9054. It can be seen that the DMA operation greatly reduces the burden on the host CPU.
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(1) Hardware improvement: Apply DDR2 storage technology and PCI bus technology to improve data throughput.
(2) Software improvement: The Kalman filter is used to replace the traditional FIR filter. Because the conversion between time domain and frequency domain is not needed, the filtering efficiency can be improved while maintaining a certain signal-to-noise ratio. 
The A/D conversion circuit is isolated from the pre-stage circuit; the second is to improve the driving capability of the pre-stage circuit. 
