This article refers to the address: http:// In the context of the rapid development of China's IT industry, the diversity of society and user demand has caused telecom equipment operators and service providers to face more and more competitive pressures. Improving competitiveness, accelerating business development capabilities, and designing products and businesses that meet market needs are key. Development in innovation and innovation in survival has become a problem that must be faced and has to be solved. This paper uses SoC design method to implement intelligent speech processing system chip that can be applied to telecom multi-service switching platform in altera high-end FPGA device. The key to system design is the unique design of the on-chip system's three-bus architecture, the design of the SDRAM (memory) controller, and the development of a shared mailbox protocol with the system host. 1 system design The design of the intelligent speech processing system is based on the Cyclone II EP2C35 [12] device. The core processing function of the system and almost all system function modules are implemented in the FPGA through the function of LogicLock. The embedded processor soft core Nios II is used as the main processor of the intelligent voice processing system to manage the operation of the board and coordinate the system. Work between modules, control their working status and operation of each peripheral; communicate with the host system of the program-controlled switch through communication sharing mailbox unit, accept system management and scheduling, download system operation from system server by means of Ethernet port Programs and a variety of different voice data. The Nios II processor is a 32-bit modified Harvard RISC soft core processor with the most 6-stage pipeline (Fetch, Decode, Execute, Memory, Align, Writeback). Up to 256 user-customizable instructions help users create an embedded system that best suits their needs. The Nios II processor cache is implemented using a simple direct-mapped continuous write structure that achieves the highest performance with minimal device resource consumption and achieves over 166 DMIPS performance in Cyclone II devices. Different from the traditional double bus structure in the Harvard system, the system design uses a three-bus structure: a dedicated high-speed bus for memory (SDRAM), a dedicated bus for ROMDISK (Flash), and a shared mailbox bus for communication with the system host. It satisfies the large-volume data transmission between ROMDISK, memory and shared mailbox bus, and ensures that the system can handle more tasks. This architecture provides concurrent execution efficiency and improves processor utilization. Fast data exchange effectively reduces waiting time and improves the efficiency of multitasking. The voice data buffer and the G.711/G.726 protocol processor provide users with data based on ITU G.711/G.726 voice compression protocol including basic voice, coaching voice, and various featured voices according to system requirements. The link provides 32-256 Mbps 16-64 kbps voice channels for the system and is provided to the system with 1-8 2 Mbps high-speed PCM links. The UART is used as the system debug interface. The system function block diagram is shown in Figure 1. 2 Business Process The main work of the intelligent voice system-on-chip is to meet the voice service type and intelligent voice service requirements of the program-controlled switch system and the IP switch system. Basic voice storage and coaching voice curing In the ROMDISK of this board, the operating system can transfer various commonly used voice data stored in ROMDISK to the three-bus mechanism after power-on initialization, operating system loading, and file system loading. In memory. At the same time, in order to meet the diversity and flexibility of the business, the system can receive various characteristic voice data from the server network: such as weather forecast, advertisement data and user's message information. The normal voice service workflow is shown in Figure 2. 3 system key part design 3.1 Memory Controller The memory controller (SDRAM) implements the operation between the Nios II processor and the memory, providing a reliable, large-capacity storage space for the system to realize multi-functional service development. The module implements functions such as initialization, refresh, and data transfer of the memory; the supported data port is 32 bits, the clock frequency is set to 100 MHz, the CAS Latency (CL) setting time is 2 clocks, and the burst length is set to 1-8. It is a design challenge to use the correct method of sampling and latching data at the right time. When the chip select signal and the read signal of the memory are valid, the read operation state is entered. After the column address is valid and the write command is valid for two clocks, the memory chip output data (CL=2) latches the data sample on the data bus on the rising edge of the clock. A data sampling latch is set in the module. According to its timing requirement, CL=2, the effective data delay output is 2CLKs, and the internal data sampling latch performs sampling latching at the clock edge time in the data valid time to complete the data acquisition from the memory. The process of the Nios II processor Avalon bus gets data from the data sampling latch in the memory controller and sends the data destination. The read operation uses an auto precharge after write burst. After the memory enters the automatic precharge operation, it is in an idle state, waiting for the start of the next state. 3.2 Shared mailbox module design The shared mailbox is a system mailbox data area that defines communication command parameters and transmission and playback commands and source code between the system and the main processing unit of the program-controlled switch system or the IP switch. This is the key to communicating properly with the system. The shared mailbox module is based on the dual-port RAM inside the FPGA. The internal communication is communicated with the Nios II processor through the Avalon switching bus. The external communication is communicated with the program-controlled switching system via a 16-bit port. The capacity is based on the system requirements. And the FPGA determines the number of PCM links to the system. Each time the system puts a part of the voice, the software records the status value. The next time from this value, continue to move a portion of the voice data from the storage area to the voice buffer space. The number of bytes written is set according to the voice buffer space. After the data is determined, a certain port and a certain amount of voice data are written into the specified RAM space in each interrupt processing cycle (voice buffer A/B area switching time). . The syntax structure is as follows: The buffer write port side is connected to the system Avalon bus, and its address space is performed in a write-through manner. The difficulty lies in reading the port side address signal. In this paper, two buffer areas are used to set up two identical storage areas in the FPGA. The address generator generates port address hopping, link address hopping and interrupt generation. The Nios II processor moves the required voice data to the address space specified by the voice data buffer according to the instructions of the program-controlled switching system host; the buffer can provide 7 bytes of space for each voice channel (N is even), and the CPU can In each voice processing interruption, N/2 bytes of voice data can be written once per voice channel. In a system frame synchronization signal FS0 cycle (125μs), 8 bits can be completed for a single voice channel, that is, one byte data conversion, using AB double buffer design mode, N/2 bytes of data needs to be N/2 The FS0 is completed, and the required time is 125μs×N/2. The period is determined according to the comprehensive response time of the system response interrupt time, the processing time of the voice data processing, and the time when the system processes other data, and the interrupt period set by the system is guaranteed. Complete business processing within the system without affecting the overall operational efficiency of the system. From the point of view of the processing of the interrupt, the system always needs to process the stacking and replying of the system important data such as the system pointer and the playback position for each interrupt generation, response and processing, and handle the same task with a short interrupt period. The system's task volume will increase accordingly. The choice of the length of the interrupt time is difficult and critical in the design. It needs to be selected according to the processing power of the processor, the time required to complete the data conversion, the processing time of the interrupt task, the RAM capacity of the FPGA, etc., using the Nios II processor. The system completes the conversion time of all (128) voice channel data, that is, the processing time of the interrupt task is 2.8×3ms. In this design, the interrupt level and interrupt period are also set according to this precondition. This design sets N=256, provides 128 channels of voice channel data, and the system needs to set the interrupt time to 16ms. The processing of the voice link PCM is completed in accordance with the ITU-G.711 protocol of the International Telecommunication Union. The G.711 protocol is a protocol for voice transmission in the PSTN network specified by the ITU, and its data rate is 64 kbps. G.726 is a standard proposed by the ITU predecessor CCITT on the basis of the G.721 and G.723 standards in 1990 for converting 64 kbps nonlinear PCM signals into 40 kbps, 32 kbps, 24 kbps, 16 kbps ADPCM signals. The G.726 standard algorithm is simple, the voice quality is high, and the voice quality is guaranteed after multiple conversions, and is widely used in the fields of voice storage and voice transmission. 4 Conclusion After the design is completed and downloaded to the FPGA, after field testing and practical application, the system fully meets the design goal. A voice sub-processor controlled by the chip is configured on each office switching module to meet 8192 switching modules. The user's requirements for the voice system prove that the intelligent multi-service system-on-chip design is successful. It can be applied to various telecommunication service systems and IP network switching systems, providing an ideal solution for enterprises to shorten time to market, reduce development risks and costs, and improve new business development capabilities. Cutting Machine,Plasma Cutting Machine,Cutting Machinery Yifa Stud Welding Equipment Co., Ltd. , http://www.yfweldingmachine.com
3.3 Speech data buffer design