Abstract: The design of an X-band frequency synthesizer, and this program will direct digital lock combination, rapid completion agility feature. introduction Modern radars place higher and higher requirements on the frequency noise of frequency synthesizers, rapid agility, flexible and variable waveform generation, and in-band spurs. The full coherent direct frequency synthesizer has high frequency stability, short frequency hopping time, the shortcoming of the direct frequency synthesizer is spurious suppression, and the amount of equipment is huge. The disadvantage of the phase-locked frequency synthesizer is that if the total frequency division ratio of the loop is too large, the output phase noise will be seriously deteriorated; and the frequency conversion speed is slow. Therefore, the combination of direct frequency multiplication and digital lock, using the fast switching speed of the switch, the frequency stability of direct frequency multiplication, and the flexibility of digital phase lock, complete the design of the program. System Block Diagram Figure 1 is a functional block diagram of the X -band frequency synthesizer. When the digital phase-locked loop works intermittently (the digital phase-locked loop is only used for frequency capture ) , the digital phase-locked loop lock time needs 40 ~ 50ms . This is because the output voltage of the loop filter is always in a saturated state when the digital phase-locked loop stops working. When the digital phase-locked loop restarts, it must go through a long recovery time to work properly. The frequency capture time of the digital phase-locked loop is too long is its shortcoming, but its digital interface is flexible and changeable, a loop can complete the needs of multiple stable frequency points, and the corresponding amount of equipment is small. The speed of the electronic switch is nS level, which can meet the needs of rapid agility. With a little design during frequency control, the advantages of the two can be effectively combined. When the switch is selected from the first ring to the second ring, the second ring is stable at the previous clock, and the agile time is determined by the switch; meanwhile, the first ring is controlled by the digital interface to change the frequency. By analogy, when the switch is selected from the second ring to the first ring at the next clock, the first ring has stabilized at the previous clock, and the agile time is determined by the switch. Thus, the difficulty of direct frequency doubling-spurious suppression is well solved.     The frequency band is expanded by the frequency doubler. The X -band upconverter is the main source of spurious signals. Because it is a broadband mixer, there will be intermodulation components in the passband. Two measures are taken here. One measure is to calculate the input signal of the mixer (fi ) And the input local oscillator signal (fL) , so that mfL ± nfi ( except fL + fi ) falls within the band as little as possible. Another measure is to use a switching filter component after the mixer, divide the broadband filter into several narrow filters, and select the corresponding filter to effectively suppress the intermodulation component. Picture 1  Frequency synthesizer block diagram Picture 2   Block diagram of digital phase lock Picture 3  In-phase parallel differential amplifier Design Points Digital phase-locked frequency synthesizer For a phase-locked synthesizer with a high operating frequency and a relatively small frequency conversion interval, if the pre-frequency division method is used, the loop frequency division is relatively large. Shifting the frequency down on the feedback branch can effectively reduce the loop frequency division ratio and help to improve the phase noise and dynamic response characteristics of the system. This is a commonly used phase-locked synthesizer. The working principle is that the reference signal and the feedback signal are compared in the PD phase. The output voltage is controlled by the loop filter LPF to suppress noise and high frequency components to control the VCO . The system achieves agile frequency conversion by controlling the frequency division ratio after the frequency shift of the feedback branch. When the loop is locked, the output frequency is f0 = (m + N / p) fi . The block diagram is shown in Figure 2 . The choice of loop gain: When selecting the loop bandwidth, the loop bandwidth is much smaller than the loop gain, so when designing, adding a primary amplifier between the frequency discriminator / phase discriminator and the loop filter will greatly The loop gain is increased to ensure the improvement of the phase noise index. The amplifier circuit is shown in Figure 3 . Because the structure of the in-phase parallel differential amplifier circuit is symmetrical, an external circuit with symmetrical parameters should be selected, that is, Rf1 = Rf2 = Rf . At this time, the differential mode gain is: It can be drawn from the above formula that the in-phase parallel differential amplifier can easily adjust the gain only by changing the Rw size. The external circuit does not require matching resistors, and the output can obtain an extremely high common mode rejection ratio. The choice of loop bandwidth: The power of the phase noise of the voltage-controlled oscillator is mainly concentrated in the low frequency part. The high-pass filtering effect of the frequency response of the error transfer function of the phase-locked loop is quite significant. At the low-frequency end of F < fn , the attenuation increases by 20 dB every 10 octave . From the above analysis, only in terms of filtering the noise of the voltage controlled oscillator, the larger the fn , the better. However, the crystal noise as the reference oscillator acts on the input of the loop phase detector. The loop exhibits a low-pass filter for the crystal noise. The filtering depends on the frequency response of the closed-loop transfer function; in the high frequency band of F < fn , the -10dB drop every 10 octave . From the above analysis, only in terms of filtering the input crystal phase noise, the smaller the loop fn, the better. In the same coordinate system, first make the phase noise spectrum of the VCO , and then make the phase noise spectrum of the crystal oscillator multiplied by N2 , you can find the intersection of the two spectral lines, as long as the fn of the loop is selected at this intersection frequency, the output phase The noise power is the smallest. As long as all noises are merged into two types, high-pass type and low-pass type, the best fn design can also be completed by the previous method . The loop filter uses an active proportional-integral filter, and its characteristics are close to the ideal integral filter. It has two independently adjustable parameters and has a lag - lead characteristic, which is conducive to the stability of the loop. Linear Frequency Modulation Signal Source Based on DDS DDS is mainly composed of phase accumulator, sin amplitude converter, D / A converter and low-pass filter (LPF), etc. The core component is the phase accumulator, as shown in Figure 4 , under the effect of the system clock, The phase accumulator completes the frequency accumulation, and takes each accumulation result as the sampling address, periodically scans the waveform memory of the sine wave, and converts the result into a voltage waveform through the D / A converter. The relationship between output frequency, frequency control word and system clock frequency is: Where: FO — frequency of the output waveform; K — frequency control word; FCLK — system clock frequency; N — phase accumulator bit length. In addition to the main spectrum, the signal synthesized by DDS has a lot of spurious components. These spurious components mainly have three sources. One is caused by the phase truncation error. This can be used to address the phase / amplitude after the phase accumulator output is truncated. It is measured by the number of bits in the conversion table. Second, the number of data bits in the waveform memory ROM is limited, which causes waveform amplitude quantization errors. This is determined by the number of output digits and DAC bits after the phase / amplitude conversion . The third is due to the DAC ’s Non-ideal characteristics, the step wave generates harmonics and spurious components at the output of the DAC . DDS chip used in the present system as AD9854 ADI's core, caused by spurious phase truncated negligible, according to the actual quantization error waveform bandwidth plus filter oversampling technique to obtain higher signal to noise ratio. For the non-ideal characteristics of DAC , in actual use, only a DAC with good linearity can be selected to improve the output signal quality of DDS . Experimental results 1 according to the block diagram shown in FIG complete X-band frequency synthesizer local oscillator path SSB phase noise power spectral density curve (fo = 9500MHz) shown in Figure 5, transmit a bandwidth of 50MHz linear FM waveform shown in Figure 6 . Picture 4  DDS functional block diagram Picture 5  Single sideband phase noise power spectral density curve Picture 6  50MHz chirp signal waveform Conclusion Digital integrated phase-locked loops have become the core of indirect frequency synthesizers because of their ease of debugging, small size, and low power consumption. DDS is widely used because of its relative bandwidth, programmable, and fully digital structure. In the verification, this program has obtained relatively satisfactory results. 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