When I recently read the blog, I found an article that can be used in the opposite direction, and I will share it with you. "Bufpll mapping error in Spartan6 development" The required clock is generated by the Clock_wizard that comes with ISE. The 750M is dedicated to the IO output clock of TMDS. The main ports are defined as follows: --Clock_gen is automatically generated by Clock_wizard. Clock_gen_inst : clock_gen And pix_clkx10_pll must add bufpll, BUFPLL is defined as follows; BUFPLL #( The schematic is shown in Figure 1. According to the above clock definition, such an error occurs during mapping: ROR: Place - ConstraintResolved NO placeable site for U2/tx_bufpll_inst ERROR: Place - SIO has over-constrained componet U2/tx_bufpll_inst to have to placeable sites. Constraints come from Total REAL TIme to Placer compleTIon: 38 secs Mapping completed. Trying many times or reporting an error by adding a PLL or deleting one of the clocks. I found it on the Internet and found a similar situation, but did not give a solution. Later I tried to add constraints to get it. Specify the physical location of bufpll directly: INST hdmi_encoder_0/hdmi_encoder_0/tx_bufpll_inst LOC= BUFPLL_X1Y5; The estimated reason is that bufpll and OSERDES cannot be mapped because they are not in a bank. Figure 1. Schematic of using OSEREDS Ref 1.S6 constraints for DDR A/D data, From Xilinx User community Forums 2. Introduction and use of Spartan-6 clock management module
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Recently, I am doing video output on Spartan6. The output interface is HDMI interface, and the required format is 720P.
The system clock has
750M (S output IO output clock, must be connected to bufpll)
75M (720P pixel clock)
150M
100M (system clock)
24M (clock required for peripherals)
The tool uses ISE12.2
Port map(
CLK_IN1 => sys_clk_in,
RESET => sys_rst,
LOCKED => LOCKED,
CLK_OUT1 => pix_clkx10_pll, --750M, need bufpll as buffer
CLK_OUT2 => pix_clk_pll, --75M
CLK_OUT3 => pix_clkx2_pll, --150M
CLK_OUT4 => sys_clk, --93.75M
CLK_OUT5 => external_clk_buf );
.DIVIDE(5)
)
Tx_bufpll_inst(
.IOCLK(tx_clkx10),
.LOCKED(LOCKED),
.LOCK(LOCK),
.PLLIN(pix_clkx10),
.GCLK(pix_clkx2),
.SERDESSTROBE(tx_serdesstrobe));
Driver constraints AND load IO constraints
Phase 4.2 IniTIal Placement for Architecture Specific Features (Checksum:fc8413ca) REAL TIme: 38 secs
Total CPU time to Placer completion: 38 secs
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.
See MAP report file "hdmi_top_map.mrp" for details.
Problem encountered during the packing phase.