Design of real-time image dehazing enhancement system based on DSP+FPGA

Image information, as one of the most intuitive information in the world of human perception, has greatly helped us to understand the world. With the continuous development of microelectronics technology in modern times, image information has gone through nothing, from analog to digital, from black and white to color, from visible light to multi-spectral, image quality (resolution, resolution, etc.) It has also been greatly improved. At the same time, human beings are constantly improving the image quality requirements. Among them, the visible image is most similar to the human eye, and its perception has a greater impact on people, so its quality requirements are higher. However, limited by the mechanism of visible light transmission and imaging, the resulting images are often plagued by problems such as fog, lack of light, etc., which cannot be overcome by the imaging process, and need to be processed afterwards. At the same time, in the field of image tracking and other applications, the time delay caused by processing the image is a fatal shortcoming to the servo system. Based on the above problems, this paper designs a real-time image dehazing enhancement system based on TI TMS320C6455+FPGA and applies it to engineering practice.

The image dehazing enhancement system is implemented by DSP+FPGA architecture. The DSP uses TI's high-speed fixed-point digital signal processing chip TMS320C6455, which is developed by TI based on the third-generation high-speed C6000 platform, clocked at 1.2GHz, on-chip memory L1P program cache 256kbit, L1D data cache 256kbit, L2 cache 16Mbit, 64-bit path EDMA controller, EMIF interface supports 16bit, 32bit, 64bit width, speed up to 100MHz. The FPGA adopts ALTERA high-end StraTIxII series chip, the model is EP2S series EP2S60-F1020C5. The chip has logic unit 60440, total RAM 318024kbit, 36 DSPblocks, 144 18bit×18bit multipliers, 12 PLLs, and 718 maximum IO numbers. Video codec is implemented using 3M chip DS90CR285 and DS90CR286.

The structural block diagram of this system is shown in Figure 1.

Figure 1 Real-time image dehazing enhancement system hardware block diagram

The image processing system based on DSP+FPGA architecture is a mature, stable and widely used hardware structure. In this structure system, FPGA is usually used as a kind of scheduling. The image processing algorithm is mainly realized by high-speed processing signal processing chip DSP. In the field of tracking and other fields, image data only needs to enter the DSP in one direction, and the corresponding parameters can be output after processing. In the real-time video image processing, a large amount of image data only needs to be input through EMIF, and the output data volume can be completed in real time. However, in the process of de-fogging enhancement, the image needs to be output not only after input processing, but also can not perform input and output time-sharing for blocking the EMIF port of the DSP chip. For continuous image data, it needs to be cached, so The corresponding data delay. In order to remove this delay, the image dehazing enhancement system only puts the parameter determination into the DSP, and the defogging enhancement algorithm is finally implemented by the FPGA. This removes the delay of image data transmission between the DSP and the FPGA, and the FPGA is pure hardware implementation, so the real-time performance is better.

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